The present invention relates to a method of design for testability and a method of design for avoiding a bus error for use in an integrated circuit.
In recent design of an integrated circuit, a tristate element is often used.
FIGS. 19(a) and 19(b) illustrate a tristate element, wherein FIG. 19(a) is a symbol standing for a tristate element in a logic circuit diagram and FIG. 19(b) is a truth table for showing the operation of the tristate element. As is shown in FIG. 19(a), the tristate element has an enable input EN in addition to a data input DIN and a data output DOUT. As is shown in FIG. 19(b), the tristate element has a function to switch, in accordance with the enable input EN, between a mode for allowing an input data to pass through to be directly output and a mode for not outputting the input data but placing the output terminal at a high impedance state. Specifically, when the enable input EN is "1", the data output DOUT is equal to the data input DIN, and when the enable input EN is "0", the data output DOUT is "Z" (namely, at the high impedance state) regardless of the logic value of the data input DIN. Hereinafter, switching of the tristate element to the mode for allowing the input data to pass through to be directly output is designated as the tristate element being turned on, and switching of the tristate element to the mode for not outputting the input data but placing the output terminal at the high impedance state is designated as the tristate element being turned off.
Any particular method of design for testability for use in a circuit designed by a scan path method and including a tristate element has not been conventionally proposed, and a circuit manufacturer has recommended design not including a tristate element to a circuit designer.
However, there conventionally arise the following problems:
First, in the conventional circuit designed by a scan path method and including a tristate element, a fault of the enable input of the tristate element cannot be detected.
For example, in order to detect the stuck-at fault on an enable input EN, the enable input EN must be set to "0"and the signal value of the data output DOUT must be observed. However, the stuck-at fault on the enable input EN cannot be detected if the data output DOUT does not connect with any external output pins of the LSI.
Furthermore, the faults in a logic circuit controlling the enable input alone cannot be detected. As a result, a fault coverage of the integrated circuit cannot be disadvantageously improved.
Also, in the case where the data outputs of plural tristate elements are connected with a common bus, there is a possibility of occurrence of a bus error such as a bus conflict due to different output data of the respective tristate elements and a bus float due to all the output terminals of the tristate elements being placed in the high impedance state. In order to avoid such a bus error, it is necessary, in testing the integrated circuit, to control the enable inputs of the respective tristate elements so that merely one of the tristate elements connected with the common bus can be in an on-state.
However, in such a case, a fault of the data inputs of the tristate elements which are not in an on-state during the test cannot be detected. In addition, faults in logic circuits connected with these data inputs alone cannot be detected. As a result, the fault coverage of the integrated circuit cannot be disadvantageously improved.